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nonvolatile memory, dual 256-position digital potentiometer data sheet ad5232 rev. c document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2001C2013 analog devices, inc. all rights reserved. technical support www.analog.com features dual-channel, 256-position resolution 10 k, 50 k, and 100 k nominal terminal resistance nonvolatile memory maintenance of wiper settings predefined linear increment/decrement instructions predefined 6 db step log taper increment/decrement instructions spi-compatible serial interface wiper settings and eemem readback 3 v to 5 v single-supply operation 2.5 v dual-supply operation 14 bytes of general-purpose user eemem permanent memory write protection 100-year typical data retention (t a = 55c) applications mechanical potentiometer replacement instrumentation: gain and offset adjustment programmable voltage-to-current conversion programmable filters, delays, and time constants programmable power supply low resolution dac replacement sensor calibration functional block diagram rdac2 rdac1 register eemem1 rdac2 register eemem2 14 bytes user eemem rdac1 addr decode serial interface power-on reset eemem control ad5232 v dd v ss gnd a1 w1 b1 a2 w2 b2 rdy wp pr s do sdi clk cs 02618-001 figure 1. general description the ad5232 device provides a nonvolatile, dual-channel, digitally controlled variable resistor (vr) with 256-position resolution. this device performs the same electronic adjustment function as a mechanical potentiometer with enhanced resolution, solid state reliability, and superior low temperature coefficient performance. the versatile programming of the ad5232 , per- ormed via a microcontroller, allows multiple modes of operation and adjustment. in the direct program mode, a predetermined setting of the rdac registers (rdac1 and rdac2) can be loaded directly from the microcontroller. another important mode of operation allows the rdacx register to be refreshed with the setting previously stored in the corresponding eemem register (eemem1 and eemem2). when changes are made to the rdacx register to establish a new wiper position, the value of the setting can be saved into the eememx register by executing an eemem save operation. after the settings are saved in the eememx register, these values are automatically transferred to the rdacx register to set the wiper position at system power-on. such operation is enabled by the internal preset strobe. the preset strobe can also be accessed externally. all internal register contents can be read via the serial data output (sdo). this includes the rdac1 and rdac2 registers, the corresponding nonvolatile eemem1 and eemem2 registers, and the 14 spare user eemem registers that are available for constant storage. the basic mode of adjustment is the increment and decrement command instructions that control the wiper position setting register (rdacx). an internal scratch pad rdacx register can be moved up or down one step of the nominal resistance between terminal a and terminal b. this step adjustment linearly changes the wiper to terminal b resistance (r wb ) by one position segment of the devices end-to-end resistance (r ab ). for exponential/ logarithmic changes in wiper setting, a left/right shift command instruction adjusts the levels in 6 db steps, which can be useful for audio and light alarm applications. the ad5232 is available in a thin, 16-lead tssop package. all parts are guaranteed to operate over the extended industrial temperature range of ?40c to +85c. an evaluation board, the eval-ad5232-10ebz , is available.
ad5232 data sheet rev. c | page 2 of 24 tabl e of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics 10 k?, 50 k?, 100 k? versions .. 3 interface timing characteristics ................................................ 5 absolute maximum ratings ............................................................ 7 thermal resistance ...................................................................... 7 esd caution .................................................................................. 7 pin configuration and function descr iptions ............................. 8 typical performance characteristics ............................................. 9 test circuits ..................................................................................... 12 theory of operation ...................................................................... 14 scratch pad and eemem programming ................................. 14 basic operation .......................................................................... 14 eemem protection .................................................................... 14 digital input/output configuration ........................................ 14 serial data interface ................................................................... 15 daisy - chaining operation ........................................................ 15 advanced control modes ......................................................... 17 using additional internal, nonvolatile eemem ................... 18 terminal voltage operating range ......................................... 18 detailed potentiometer operation .......................................... 18 programming the variable resistor ......................................... 19 programming the potentiometer divider ............................... 20 operation from dual supplies ................................................. 20 application programming examples ...................................... 20 equipment customer start - up sequence for a pcb calibrated unit with protected settings ................ 21 flash/eemem reliability .......................................................... 21 evaluation board ........................................................................ 21 outline dimensions ....................................................................... 22 ordering guide .......................................................................... 22 revision history 11/13 rev. b to rev. c change d t 16 from 25 ms (max) to 25 ms (typ) ; table 2 ............... 5 changes to ordering guide .......................................................... 22 0 9 /11 rev. a to rev. b change to resistor noise voltage parameter in table 1 ............. 4 10 /09 rev. 0 to rev. a updated format .................................................................. universal changes to data sheet title ............................................................ 1 changes to features section ............................................................ 1 changes to applications section ..................................................... 1 change to wiper resistance parameter , table 1 ........................... 3 changes to cs rise to rdy fall time parameter, table 2 ........... 5 changes to figure 2 and figure 3 .................................................... 6 changes to figure 24 ...................................................................... 12 added figure 32 ............................................................................. 13 changes to serial data interface section .................................... 15 changes to programming the variable resistor section .......... 19 c hanges to ordering guide .......................................................... 22 10/01 revision 0: initial version
data sheet ad5232 rev. c | page 3 of 24 s pecifications electrical character istics 10 k ? , 50 k ?, 100 k ? versions v dd = 3 v 10% or 5 v 10% and v ss = 0 v, v a = +v dd , v b = 0 v, ? 40c < t a < +85c , unless otherwise noted. table 1 . parameter symbol conditions min typ 1 max unit dc characteristics, rheostat mode specifications a pply to a ll vrs resistor differential nonlinearity 2 r - dnl r wb , v a = nc ? 1 1/2 +1 lsb resistor nonlinearity 2 r - inl r wb , v a = nc ? 0.4 +0.4 % fs nominal resistor tolerance ? r ab ? 40 +20 % res istance temperature coefficient ? r ab / ? t 600 ppm/c wiper resistance r w i w = 100 a, v dd = 5.5 v, c ode = 0x 1e 5 0 100 ? i w = 1 00 a, v dd = 3 v, c ode = 0x 1e 200 ? potentiometer divider modes resolution n 8 bits differential nonlinearity 3 dnl ? 1 1 /2 +1 lsb integral nonlinearity 3 inl ? 0.4 +0.4 % fs voltage divider t emperature coefficient ? v w / t code = half s cale 15 ppm/c full - scale error v wfse code = full s cale ? 3 0 % fs zero - scale error v wzse code = zero s cale 0 3 % fs resistor terminals terminal voltage range 4 v a , v b , v w v ss v dd v capacitance ax, bx 5 c a , c b f = 1 mhz, m easured to gnd, code = half - scale 45 pf capacitance wx 5 c w f = 1 mhz, m easured to gnd, code = half s cale 60 pf common - mode leakage current 5 , 6 i cm v w = v dd /2 0.01 1 a digital inputs and outputs input logic high v ih with r espect to gnd, v dd = 5 v 2.4 v input logic low v il with r espect to gnd, v dd = 5 v 0.8 v input logic high v ih with r espect to gnd , v dd = 3 v 2.1 v input logic low v il with r espect to gnd, v dd = 3 v 0.6 v input logic high v ih with r espect to gnd, v dd = +2.5 v, v ss = ?2.5 v 2.0 v input logic low v il with r espect to gnd, v dd = +2.5 v, v ss = ? 2.5 v 0.5 v outpu t logic high (sdo and rdy) v oh r pull - up = 2.2 k ? to 5 v 4.9 v output logic low v ol i ol = 1.6 ma, v logic = 5 v 0.4 v input current i il v in = 0 v or v dd 2.5 a input capacitance 5 c il 4 pf powe r supplies single - supply power range v dd v ss = 0 v 2.7 5.5 v dual - supply power range v dd /v ss 2.25 2.75 v positive supply current i dd v ih = v dd or v il = gnd 3.5 10 a programming mode current i dd(pg) v ih = v dd or v il = gnd 35 ma read mode current 7 i dd(xfr) v ih = v dd or v il = gnd 0.9 3 9 ma negative supply current i ss v ih = v dd or v il = gnd, v dd = +2.5 v, v ss = ? 2.5 v 3.5 10 a power dissipation 8 p diss v ih = v dd or v il = gnd 0.018 0.05 mw power supply sensitivity 5 pss ? v dd = 5 v 10% 0.002 0.01 %/%
ad5232 data sheet rev. c | page 4 of 24 parameter symbol conditions min typ 1 max unit dynamic characteristics 5 , 9 bandwidth ? 3 db, bw_10k ? , r = 10 k ? 500 khz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz, r ab = 10 k? 0.022 % v a = 1 v rms, v b = 0 v, f = 1 khz, r ab = 50 k?, 100 k? 0.045 % v w settling time t s v dd = 5 v, v ss = 0 v, v a = v dd , v b = 0 v, 0.65/3/6 s v w = 0.50% e rro r b and, code 0x 00 to code 0x 80 f or r ab = 10 k?/50 k?/100 k? resistor noise voltage e n_wb r wb = 5 k ? , f= 1 khz 9 n v/ hz crosstalk (c w1 /c w2 ) c t v a = v dd , v b = 0 v, m easure v w with ?5 nv - sec a djacent vr making full - scale code c hange analog crosstalk (c w1 /c w2 ) c ta v a1 = v dd , v b1 = 0 v, m easure v w1 with v w2 = ?70 db 5 v p - p @ f = 10 khz ; code 1 = 0x80; code 2 = 0xff flash/ee memory reliability enduranc e 10 100 kcycles data retention 11 100 years 1 typical parameters represent average readings at 25 c and v dd = 5 v. 2 resistor posit ion nonlinearity ( r - inl ) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r - dnl measures the relative step change from ideal between successive tap positions. parts are guarantee d monotonic. i w ~ 50 a @ v dd = 2.7 v and i w ~ 400 a @ v dd = 5 v for the r ab = 10 k? version, i w ~ 50 a for the r ab = 50 k? version , and i w ~ 25 a for the r ab = 100 k? version (s ee figure 22) . 3 inl and dnl are measured at v w wi th the rdac x configured as a potentiometer divider similar to a voltage output digital - to - analog converter. v a = v dd and v b = v ss . dnl specification limits of 1 lsb maximum are guaranteed m onotonic operating conditions (s ee figure 23) . 4 the a, b , and w resistor terminals have no limitations on polarity with respect to each other. dual supply operation enables ground - referenced bipolar signal adjustment. 5 guaranteed by design; not subject to production test. 6 common - mode leakage current is a meas ure of the dc leakage from any a, b, or w terminal to a common - mode bias level of v dd /2. 7 tr ansfer (xfr) m ode current is not continuous. current is consumed while the eemem x locations are read and t ransferred to the rdacx register (s ee figure 13 ) . 8 p diss is calculated from (i dd v dd ) + (i ss v ss ). 9 all dynamic characteristics use v dd = +2.5 v and v ss = ? 2.5 v, unless otherwise noted. 10 endurance is qualified to 100,000 cycles per jedec st d . 22, method a117 and measured at ? 40c, +25c, and +85c. typical endurance at +25c is 700,000 cycles. 11 the r etention lifetime equivalent at junction temperature (t j ) = 55c, as per jedec std. 22, method a117. retention lifetime, based on an activation energy of 0.6 ev, derates with junction temperature as shown in figure 44 in the f lash/eemem reliability section. the ad5232 contains 9,646 transistors. die size = 69 mil 115 mil, 7,993 sq. mil.
data sheet ad5232 rev. c | page 5 of 24 interface timing characteristics all input control voltages are specified with t r = t f = 2.5 ns (10% to 90% of 3 v) and are timed from a voltage level of 1.5 v. switching characteristics are measured usi ng both v dd = 3 v and v dd = 5 v. table 2 . parameter 1 , 2 symbol conditions min typ 3 max unit clock cycle time (t cyc ) t 1 20 ns cs setup time t 2 10 ns clk shutdown time to cs rise t 3 1 t cyc input clock pulse width t 4 , t 5 clock level high or low 10 ns data setup time t 6 from positive clk transition 5 ns data hold time t 7 from positive clk transition 5 ns cs to sdo - spi line acquire t 8 40 ns cs to sdo - spi line release t 9 50 ns clk to sdo propagation delay 4 t 10 r p = 2.2 k ? , c l < 20 pf 50 ns clk to sdo data hold time t 11 r p = 2.2 k ? , c l < 20 pf 0 ns cs high pulse width 5 t 12 10 ns cs high to cs high 5 t 13 4 t cyc rdy rise to cs fall t 14 0 ns cs rise to rdy fall time t 15 0.15 0.3 ms store/read eemem time 6 t 16 applies to command instruction 2, command instruction 3, and command instruction 9 25 ms cs rise to clock ris e/fall setup t 17 10 ns preset pulse width (asynchronous) t prw not shown in timing diagram 50 ns preset response t ime to rdy high t presp pr pulsed low to refresh wiper positions 70 s 1 guaranteed by design; not subject to production test. 2 see the timing diagrams section for the location of measured values. 3 typicals represent average readings at 25 c and v dd = 5 v. 4 propagation delay depends on the value of v dd , r pull - up , and c l . 5 valid for commands that do not activate the rdy pi n. 6 rdy pin low only for command instruction 2, command instruction 3, command instruction 8, command instruction 9, command inst ruction 10, and the pr hardware pulse: cmd_8 ~ 1 ms, cmd_9 = cmd_10 ~ 0.12 ms, and cmd_2 = cmd_3 ~ 20 ms. de vice operation at t a = ? 40c and v dd < 3 v extends the save time to 35 ms.
ad5232 data sheet rev. c | page 6 of 24 timing diagrams cpol = 1 t 12 t 13 t 3 t 17 t 9 t 11 t 5 t 4 t 2 t 1 clk t 8 b16* b15 (msb) b15 (msb) high or low high or low b15 b0 b0 (lsb) b0 (lsb) rdy cpha = 1 t 10 t 7 t 6 t 14 t 15 t 16 sdo sdi 02618-002 cs notes 1. b24 is an extra bit that is not defined, but it is usually the lsb of the character that was previously transmitted. 2. the cpol = 1 microcontroller command aligns the incoming data to the positive edge of the clock. figure 2. cpha = 1 t 12 t 13 t 3 t 17 t 9 t 11 t 5 t 4 t 2 t 1 clk cpol = 0 t 8 sdo b15 b0 high or low high or low sdi rdy cpha = 0 t 10 t 7 t 6 t 14 t 15 t 16 * 02618-003 cs b15 (msb in) b15 (msb) b0 (lsb) b15 (msb out) b0 (lsb) b0 (lsb) notes 1. this extra bit is not defined, but it is usually the msb of the character that was just received. 2. the cpol = 0 microcontroller command aligns the incoming data to the positive edge of the clock. figure 3. cpha = 0
data sheet ad5232 rev. c | page 7 of 24 absolute maximum rat ings t a = 25 c, unless otherwise noted. table 3 . parameter rating v dd to gnd ? 0.3 v, +7 v v ss to gnd +0.3 v, ? 7 v v dd to v ss 7 v v a , v b , v w to gnd v ss ? 0.3 v, v dd + 0.3 v a x ? b x , a x ? w x , b x ? w x intermittent 1 20 ma continuous 2 ma digital inputs and output voltage to gnd ? 0.3 v, v dd + 0.3 v operating temperature range 2 ? 40c to +85c maximum junction temperature (t j max ) 150c s torage temperature range ? 65c to +150c lead temperature, soldering vapor phase (60 sec) 215 c infrared (15 sec) 220c package power dissipation (t j max ? t a )/ ja 1 maximum terminal current is bounded by the maximum current handling of the switche s, maximum power dissipation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance. 2 includes programming of nonvolatile memory. stresses above those listed under absolute maximum ratings may caus e permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating con ditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 4 . thermal resistance pac kage type ja jc unit 16- lead tssop (ru - 16) 150 28 c/w esd caution
ad5232 data sheet rev. c | page 8 of 24 pin configuration an d function descriptions 1 2 3 4 5 6 7 8 sdi sdo gnd w1 a1 v ss clk b1 16 15 14 13 12 1 1 10 9 cs pr wp w2 b2 a2 v dd rd y ad5232 t op view (not to scale) 02618-004 figure 4 . pin configuration table 5 . pin function descriptions pin no. mnemoni c description 1 clk serial input register clock. shifts in one bit at a time on positive clock edges. 2 sdi serial data input. the msb is loaded first. 3 sdo serial data output. this o pen - drain output requires an external pull - up resistor. comm and instruction 9 and command instruction 10 activate the sdo output (s ee table 8 ) . other commands shift out the previously loaded sdi bit pat tern delayed by 16 clock pulses, allowing daisy - chain operation of multiple packages. 4 gnd gro und , logic ground reference. 5 v ss negative power supply. connect to 0 v for single - supply applications. 6 a1 terminal a of rdac1. 7 w1 wiper terminal w of rdac1, addr (rdac1) = 0x 0 . 8 b1 terminal b of rdac1. 9 b2 terminal b of rd ac2. 10 w2 wiper terminal w of rdac2, addr (rdac2) = 0x 1 . 11 a2 terminal a of rdac2. 12 v dd positive power supply. 13 wp write protect . when active low, wp prevents any changes to the present regist er contents, except pr , command instruction 1 , and command instruction 8, which refresh the rdac x register from eemem. execute a n nop instruction (command instruction 0) before returning wp to logic high. 14 pr hardware override preset. refreshes the scratch pad register with current contents of the eemem x r egister. factory default loads m idscale 0x 80 until eemem x is loaded with a new value by the user ( pr is acti vated at the logic high transition). 15 cs serial register chip select , active low. serial register operation takes place when cs returns to logic high. 16 rdy ready. this a ctive - high , open - drain output requires a pull - up resi stor. identifie s completion of com mand instruction 2, command instruction 3, command instruction 8, command instruction 9, command instruction 10, and pr .
data sheet ad5232 rev. c | page 9 of 24 typical performance characteristics 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 ?0.25 ?0.50 ?0.75 ?1.00 ?1.25 ?1.50 ?1.75 ?2.00 0 64 128 192 256 digital code inl error (lsb) 02618-005 v dd = 2.7v v ss = 0v in l t a = ?40c in l t a = +85c in l t a = +25c figure 5 . inl vs. code; t a = ? 40c, +25c, +85c overlay 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 ?0.25 ?0.50 ?0.75 ?1.00 ?1.25 ?1.50 ?1.75 ?2.00 0 64 128 192 256 digital code dnl error (lsb) 02618-006 v dd = 2.7v v ss = 0v dn l t a = ?40c dn l t a = +85c dn l t a = +25c figure 6 . dnl vs. code; t a = ? 40c, +25c, +85c overlay 0.20 0.15 0.10 0.05 0 ?0.05 ?0.10 ?0.15 ?0.20 0 32 64 96 128 160 192 224 256 code (decimal) r-dnl (lsb) 02618-007 v dd = 5.5v v ss = 0v t a = 25c figure 7. r - dnl vs. code ; r ab = 10 k?, 50 k?, 100 k ? overlay 2000 1500 1000 500 0 0 32 64 96 128 160 192 224 256 code (decimal) rheostat mode tempco (ppm/c) 02618-008 v dd = 5v t a = ?40c/+85c v a = no connect r wb measured figure 8 . r wb / t vs. code ; r ab = 10 k?, v dd = 5 v 70 60 50 40 30 20 10 0 ?10 0 32 64 96 128 160 192 224 256 code (decimal) potentiometer mode tempco (ppm/c) 02618-009 v dd = 5v t a = ?40c/+85c v a = 2v v b = 0v figure 9 . v wb / t vs. code ; r ab = 10 k?, v dd = 5 v 1 0.1 0.01 0.001 ?50 ?35 ?20 ?5 10 temperature (c) 25 40 55 70 85 i cm (a) 02618-010 v dd = +2.5v v ss = ?2.5v v cm = 0v figure 10 . i cm vs. temperature (see figure 30 )
ad5232 data sheet rev. c | page 10 of 24 4 2 0 ?50 ?35 ?20 ?5 10 temperature (c) 25 40 55 70 85 i dd (a) 02618-011 v dd = 5.5v v dd = 2.7v figure 11. i dd vs. temperature 02618-012 ch1 5.00v ch2 5.00v ch3 5.00v ch4 10.00v m 2.00ms cs clk sdi i dd 2ma/div 1 4 3 2 t figure 12. i dd vs. time (save) program mode 02618-013 ch1 5.00v ch2 5.00v ch3 5.00v ch4 10.00v m 2.00ms cs clk sdi 1 4 3 2 t * supply current returns to minimum power consumption if command instruction 0 (nop) is executed immediately after command instruction 1 (read eemem). i dd * 2ma/div figure 13. i dd vs. time read mode 12 6 0 ?6 ?12 ?18 ?24 ?30 ?36 ?42 1k 10k 100k 1m frequency (hz) gain (db) 02618-014 v in = 100mv rms v dd = +2.5v v ss = ?2.5v r l = 1m ? t a = +25c f ?3db = 500khz, r = 10k ? f ?3db = 45khz, r = 100k ? f ?3db = 95khz, r = 50k ? figure 14. ?3 db bandwidth vs. resistance 10 1 0.1 0.01 0.001 10 100 1k 10k 100k frequency (hz) thd + noise (%) 02618-015 v dd = 5v t a = 25c filter = 22khz r ab = 10k ? r ab = 50k ? , 100k ? figure 15. total harmonic distortion + noise vs. frequency 70 80 90 100 110 60 50 40 30 20 10 0 0 32 64 96 128 160 192 224 256 code (decimal) r w ( ? ) 02618-016 v dd = 2.7v t a = 25c figure 16. wiper on resistance vs. code
data sheet ad5232 rev. c | page 11 of 24 0 ?6 ?12 ?18 ?24 ?30 ?36 ?42 ?48 ?54 ?60 1k 10k 100k 1m frequency (hz) gain (db) 02618-017 r ab = 10k? 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 v dd = +2.7v v ss = ?2.7v v a = 100mv rms t a = 25c v a figure 17 . gain vs. frequency vs. code, r ab = 10 k? 0 ?6 ?12 ?18 ?24 ?30 ?36 ?42 ?48 ?54 ?60 1k 10k 100k 1m frequency (hz) gain (db) 02618-018 r ab = 50k? v dd = +2.7v v ss = ?2.7v v a = 100mv rms t a = 25c v a 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 figure 18 . gain vs. frequency vs. code, r ab = 50 k? 0 ?6 ?12 ?18 ?24 ?30 ?36 ?42 ?48 ?54 ?60 1k 10k 100k 1m frequency (hz) gain (db) 02618-019 r ab = 100k? v dd = +2.7v v ss = ?2.7v v a = 100mv rms t a = 25c v a 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 figure 19 . gain vs. frequency vs. code, r ab = 100 k? 80 60 40 20 0 1k 10k 100k 1m frequency (hz) psrr rejection (db) 02618-020 r ab = 100k? r ab = 10k? r ab = 50k? v dd = 5.5v 100mv ac v ss = 0v v b = 5v v a = 0v measure a t v w with code = 0x80 t a = 25c figure 20 . psrr vs. frequency 120 100 80 60 40 20 1 10 100 frequency (khz) c ta analog crosstalk rejection (db) 02618-021 r ab = 100k? r ab = 10k? r ab = 50k? v dd = v a2 = +2.75v v ss = v b2 = ?2.75v v in = +5v p- p t a = 25c figure 21 . analog crosstalk vs. frequency (see figure 31 )
ad5232 data sheet rev. c | page 12 of 24 test circuits figure 22 to figure 32 define the test conditions that are used in the s pecifications section. a w b nc dut nc = no connect 02618-022 i w v ms figure 22 . resistor position nonlinearity error (rheostat operation; r - inl, r - dnl) a w b dut v+ 02618-023 v+ = v dd 1lsb = v+/2 n v ms figure 23 . potentiometer divider nonlinearity error (inl, dnl) a w b dut i w = v dd /r nomina l 02618-024 v ms1 v w r w = [v ms1 ? v ms2 ]/i w v ms2 figure 24 . wiper resis tance a w b v+ = v dd 10% pss (%/%) = ~ v a v+ 02618-025 psrr (db) = 20 log v ms v dd ( ) v ms % v dd % v ms v dd figure 25 . power supply sensitivity (pss, psrr) offset bias ab dut w 5v op279 02618-026 v out v in offset gnd figure 26 . inverting gain offset bias ab dut w 5v 02618-027 v out v in offset gnd op279 figure 27 . noninverting gain a b dut w +15v op42 ?15v 2.5v 02618-028 v out v in offset gnd figure 28 . gain vs. frequenc y + ? dut code = 0x00 0.1v v ss to v dd w b a a = nc 02618-029 r sw = 0.1v i sw i sw figure 29 . incremental on resistance
data sheet ad5232 rev. c | page 13 of 24 dut w b nc nc gnd a nc = no connect 02618-030 i cm v cm v ss v dd figure 30 . common - mode leakage current 02618-031 a1 rdac1 rdac2 w1 nc b1 a2 w2 b2 c t a = 20 log [v out /v in ] nc = no connect v in v out v ss v dd figure 31 . analog crosstalk 02618-032 200 a i o l 200 a i oh v oh (min) or v ol (max) t o output pin c l 50pf notes 1. the diode bridge test circuit is equi v alent t o the applic a tion circuit with r pull-up of 2.2k?. figure 32 . load circuit for mea suring v oh and v ol
ad5232 data sheet rev. c | page 14 of 24 theory of o peration the ad5232 digital potentiometer is designed to operate as a true variable resistor replacement device for analog signals that remain within the termin al voltage range of v ss < v term < v dd . the basic voltage range is limited to a |v dd ? v ss | < 5.5 v. the digital potentiometer wiper position is determined by the rdac x register contents. the rdac x register acts as a scratch pad register , allowing as many value changes as necessary to place the poten - tiometer wiper in the correct position. the scratch pad register can be programmed with any position value using the standard spi serial interface mode by loading the complet e representative data - word. when a desirable position is found, this value can be saved into a corresponding eemem x regis ter. thereafter , the wiper position is always set at that position for any future on - off - on power supply sequence. the eemem save process takes approx - imately 25 ms. d uring this time, the shift register is locked, preventing any changes from taking place. the rdy pin indicates the completion of this eemem save. scratch pad and eeme m programming the scratch pad register (rdac x register) directly controls the position of the digital potentiometer wiper. when the scratch pad register is loaded with all 0 s, the wiper is connected to terminal b of the variable resistor. when the scratch pad register is loaded with midscale code (1/2 of full - scale position), the wiper is connected to the middle of the variable resistor. when the scratch pad is loaded with full - sc a le code, which is all 1s, the wiper connect s to terminal a. because the scratch pad register is a standard logic register, there is no restriction on the number of changes allowed. the eemem x registers have a program erase/write cycle limitation that is de scribed in the flash/eemem reliability section. basic operation the basic mode of setting the variable resistor wiper position ( by programming the scratch pad register) is accomplished by loading the seria l data input register w ith command i nstruc - tion 11, which includes the desired wiper position data. when the desired wiper position is found, the user loads the seria l data input register with command i nstruction 2, which copies the desired wiper position data into the correspon ding non - volatile eemem x register. after 25 ms, the wiper position is permanently stored in the corresponding nonvolatile eemem location. table 6 provides an application programming example listing the sequence of serial data input (sdi) words and the corresponding serial data output appearing at the serial data output ( sdo ) pin in hexadecimal format. at system power - on, the scratch pad register is refreshed with the last value saved in the eemem x register. the factory preset eemem value is midscale. the scratch pad (wiper) register can be refreshed with the current contents of the nonvolatile eemem x register under hardware control by pulsing the pr pin. t he applic ation programming example shown in table 6 lists two digital potentiometers set to independent data values. t he wiper positions are then saved in the corresponding nonvolatile eemem x registers. table 6 . application programming example sdi sdo action 0x b040 0x xxxx 1 loads 0x40 data into the rdac1 register; wiper w1 moves to 1/4 full - scale position. 0x 20xx 1 0x b040 saves a copy of the rdac1 register contents into the c orrespondi ng eemem 1 register. 0x b180 0x 20xx 1 loads 0x 80 data into the rdac2 register; w iper w2 moves to 1/2 full - scale position. 0x 21xx 1 0x b180 saves a copy of the rdac2 register co ntents into the corresponding eemem2 r egister . 1 x = dont care . note that the pr pulse first sets the wip er at midscale when it is brou ght to logic 0 . then, on the positive transition to logic high, it reloads the dac wiper register with the contents of eemem x . many additional advanced programming commands are avail - able to simplify the variable resistor adjustment process. for example, t he wiper position can be changed , one step at a time , by using the software controlled increment/decrement command instruction s . the wiper position can be also be changed, 6 db at a time , by using the shift left/r ight command instruction s . after an increme nt, d ecrement, or s hift command instruction is loaded into the shift register, subsequent cs strobes repeat this command instruction . this is useful for push - button control appli - cations (s ee the advanced co ntrol modes section) . the sdo pin is available for daisy chaining and for readout of the internal register contents. the serial inp ut data register uses a 16 - bit instruction/address/data - word . eemem protection the w rite protect ( wp ) pin disables any changes of the scratch pad register contents , regardless of the software commands, except that the eemem setting can be refreshed using instruction command 8 and pr . therefore, the wp pin prov ides a hardware eemem protection feature. execute a n nop command (com - mand instruction 0) before returning wp to logic high. d igital i nput /o utput c onfiguration all digital inputs are esd protected , high input impedance that can be dr iven directly from most digital sources. the pr and wp pins , which are active at logic low, must be biased to v dd if they are not being used. no internal pull - up resistors are present on any digital input pins. the sdo and rdy pins are open - drain , digital outputs when pull - up resistors are needed , but only if these functions are in use. a resi stor value in the range of 1 k? to 10 k? optimizes the power and switching speed trade - off.
data sheet ad5232 rev. c | page 15 of 24 serial data interfac e the ad5232 contains a 4 - wire spi - compatible digital interface (sdi, sdo, cs , and clk) and uses a 16 - bit serial data - word that is loaded m sb first. the format of the spi - compatibl e word is shown in table 7 . the chip select ( cs ) pin must be held low until the complete data - word is loaded into the sdi pin. when cs returns high, the serial data - word is decoded acc ording to the instructions in table 8 . the command bits (cx) control the operation of the digital potentiometer. the address bits (ax) determine which register is activated. the data bits (dx) are the values that are loaded into th e decoded register. table 9 provides an address map of the eemem locations. the last command instruction executed prior to a period of no prog ramming activity should be the no o perat ion (nop) command instruction (com - mand instruc tion 0) . this instruction place s the internal logic circuitry in a minimum power dissipation state. 02618-033 counter clk sdi 5v sdo gnd pr w p ad5232 cs valid command serial register command processor and address decode r pull-u p figure 33 . equivalent digital input/ output logic the ad5232 has an i nternal coun ter that counts a multiple of 16 bits (per frame) for proper operation. for example, the ad5232 works with a 16- bit or 32 - bit word, but it cannot work properly with a 15 - bit or 17 - bit word . t o prevent data from mislocking (due to noise, f or example), the counter resets if the count is not a multiple of 4 when cs goes high , b ut the data remains in the register if the count is a multiple of 4 . in addition, the ad5232 has a subtle feature whereby , if cs is pulsed without clk and sdi , the part repeats the previous command (except during power - up). as a result, care must be taken to ensure that n o excessive noise exists in the clk or cs line that may alter the effective number of bits pattern. the equivalent serial data input and output logic is shown in figure 33 . the open - drain sdo is disabled whenever cs is logic high. the spi interface can be used in two slave modes : cpha = 1, cpol = 1 ; and cpha = 0, cpol = 0. cpha and cpol refer to the control bits that dictate spi timing in the following micro - pro cessors and microconverter ? de vices : the aduc812 and the aduc824 , the m68hc11, and the mc68hc16r1/ 916r1. esd protection of the digital inputs is shown in figure 34 and figure 35. gnd 02618-034 inputs 300? v dd logic pins ad5232 figure 34 . equivalent esd digital input protection gnd 02618-035 inputs 300? v dd wp ad5232 figure 35 . equivalent wp input protection daisy - chaining operation the sdo pin serves two purposes : i t can be used to read back the contents of the wiper setting and the eemem using c ommand i nstruction 9 and command instruction 10 (see table 8 ) , or it can be u sed for daisy - chaining multiple devices. the remaining com - mand instruction s are valid for daisy - chaining multiple devices in simultaneous op erations. daisy chaining minimizes the number of port pins required from the controlling ic ( see figure 36 ). the sdo pin contains an open - drain n - c hannel fet that requires a pull - up resistor if this function is used. as shown in figure 36, users must tie the sdo pin of one package to the sdi pin of the next package. users may need to increase the clock period because the pull - up resistor and the capacitive loading at the sd o - to - sdi interface may require additional time delay between subs equent packages. if two ad5232 s are daisy - chained, 32 bits of data are required. the first 16 bits go to u2 , and the second 16 bits with the same format go to u1. the 16 bits are formatted to contain the 4 - bit instruction, fol lowed by the 4 - bit address, followed by the eight b its of data. the cs pin should be kept low until all 32 bits are locked into their respective serial registers. the cs pin is then pulled high to complete the operation. sdi sdo clk clk sdi sdo ad5232 u1 ad5232 u2 02618-036 cs cs v dd microconverter r p 2.2k? figure 36 . da isy - chain configuration using the sdo
ad5232 data sheet rev. c | page 16 of 24 command bits are identified as cx, address bits are ax, and data bits are dx. the c ommand instruction codes are defined in table 8 . the sdo output shifts out the last eight bits of data c locked into the serial reg ister for daisy - chain operation, with the following exception: after command i nstruction 9 or com - mand instruction 10, the selected internal register data is present in data byte 0. the command instructions following command instr uction 9 and command instruction 10 must be full 16 - bit data - word s to completely clock out the contents of the serial register. the rdac x register is a volatile scratch pad register that is refreshed at power - on from the corresponding nonvol - atile eemem x r egister. the increment, decrement, and shift command instructions ignore the contents of data byte 0 in the shift register. execution of the o peration noted in table 8 occurs when the cs strobe returns to l ogic high. execution of a n nop instruction minimizes power dissipation. table 7 . 16 - bit serial data word msb lsb b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 c3 c2 c1 c0 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 table 8 . instruction/operation truth table comm . inst. no. instruction byte 1 data byte 0 b15 b8 b7 b0 c3 c2 c1 c0 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 operation 0 0 0 0 0 x x x x x x x x x x x x no o peration (nop). do nothing. 1 0 0 0 1 0 0 0 a0 x x x x x x x x write contents of eemem (a0) to the rdac (a0) register. this com - mand leaves the device in the read program power state. to return the part t o the idle state, perform command i nstruction 0 (nop) . 2 0 0 1 0 0 0 0 a0 x x x x x x x x save wiper setting . write contents of rdac (addr) to eemem (a0). 3 0 0 1 1 addr d7 d6 d5 d4 d3 d2 d1 d0 write contents of serial register data byte 0 to eemem (addr). 4 0 1 0 0 0 0 0 a0 x x x x x x x x decrement 6 db right shift con - tents of rdac (a0). s tops at all 0s. 5 0 1 0 1 x x x x x x x x x x x x decrement a ll 6 db right shift contents of all rdac r egisters. stops at all 0s. 6 0 1 1 0 0 0 0 a0 x x x x x x x x decrement contents of rdac (a0) by 1. stops at all 0s. 7 0 1 1 1 x x x x x x x x x x x x decrement contents of all rdac r egisters by 1. stops at all 0s. 8 1 0 0 0 0 0 0 0 x x x x x x x x reset . load all rdacs with their corresponding , previously saved eemem values. 9 1 0 0 1 addr x x x x x x x x write contents of eemem(addr) to serial register data byte 0. 10 1 0 1 0 0 0 0 a0 x x x x x x x x write contents of rdac (a0) to serial register da ta byte 0. 11 1 0 1 1 0 0 0 a0 d7 d6 d5 d4 d3 d2 d1 d0 write contents of serial register data byte 0 to rdac (a0). 12 1 1 0 0 0 0 0 a0 x x x x x x x x increment 6 db left shift contents of rdac (a0). stops at all 1s. 13 1 1 0 1 x x x x x x x x x x x x increment all 6 db left shift contents of all rdac registers. stops at all 1s. 14 1 1 1 0 0 0 0 a0 x x x x x x x x increment contents of rdac (a0) by 1. stops at all 1s. 15 1 1 1 1 x x x x x x x x x x x x increment con tent s of all rdac r egisters by 1. stops at all 1s.
data sheet ad5232 rev. c | page 17 of 24 advanced control mod es the ad5232 digital potentiometer contains a set of user program - ming features to address the wide variety of application s avail - able to these universal adjustment devices. key programming features include the following : ? independently programmable read and write to all registers ? simultaneous refresh of all rdac wiper registers from corresp onding internal eemem registers ? incr ement and decrement command instructio ns for each rdac wiper register ? left and right bit shift of all rdac wiper register s to achieve 6 db level changes ? nonvolatile storage of the present scratch pad rdac x register values into the corresponding eemem x regi ste r ? fourteen extra bytes of user - addressable , electrical erasable memory increment and decrement commands the increment and decrement command instructions ( command instruction 14, command instruction 15, command instruction 6, and command instruction 7) a re useful for the basic servo adjust - ment application. these command s simplify microcontroller software coding by eliminating the need to perform a readbac k of the current wiper position and then add a 1 to the register cont ents using the microcontroller a dder. the microcontroller sends an increment command instruction ( command instruc - tion 14) to the digital potentiometer, which automatically move s the wiper to the next resistance segment position. the master increment command instruction ( command instruct ion 15) move s all potentiometer wipers by one position from their present position to the next resistor segment position. the direction of movement is referenced to terminal b. thus, each command instruction 15 move s the w iper tap position farther from t er minal b. logarithmic taper mode adjustment programming inst ructions allow decrement and increment wiper position control by an individual poten tiometer or in a ganged potentiometer a rrangement , where both wiper positions are changed at the same time. these settings are activated by the 6 db decrement and 6 db increment command i nstructions (command instruction 4 and command instruction 5, and command instruction 12 and command instruction 13, respectively ). for example , starting with the wiper con nected to t erminal b, executing nine increment instructions ( command instruction 12) move s the wiper in 6 db steps from the 0% of the r ba (t erminal b) position to the 100% of the r ba position of the ad5232 8 - bit potentiometer. the 6 db increment instruction doubles the value of the rdac x register contents each time the command is executed. when the wiper position is greater than midscale, the last 6 db increment command instruction cause s the wiper to go to the full - scale 255 code position. any ad di - tional 6 db instruction does not chan ge the wiper position from full scale (rdac x register code = 255). figure 37 illustrates the operation of the 6 db shifting function on the individual rdac x register data bits for the 8 - bit ad5232 example. each line going down the table represents a successive shift operation. note that the left s hift 12 and left shift 13 com - mand instructions were modified so that if the data in th e rdac x register is equal to 0 and is l eft shifted, it is then set to c ode 1. in addition , the left shift commands were modified so that if the data in the rdac register is greater than or equal to mi dscale and is le ft shifted, the data is then set to full scale. this makes the left shift function as clo se to ideally logarithmic as possible . the right s hift 4 and right shift 5 command instructions are ide al only if the lsb is 0 (that is, ideal logarithmic, with no er ror). if the lsb is a 1, the right shift f unction generates a linear half - lsb error that translates to a code - dependent logarithmic error for odd codes only , as shown in figure 38. the plot shows the errors of the odd codes. left shift 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000 1111 1111 1111 1111 right shift 1111 1111 0111 1111 0011 1111 0001 1111 0000 0111 0000 0011 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 left shift (+6db) right shift (?6db) 02618-037 fi gure 37 . detail left and right shift function actual conformance to a logarithmic curve between the data contents in the rdac x register a nd the wiper position for each right s hift 4 and right shift 5 command execution contains an error only for the odd codes. the e ven codes are ideal , with the excep tion of zero right shift or greater than half - scale left shift. figure 38 shows plots of log_error, that is , 20 log 10 (error/code) . for examp le, code 3 log_e rror = 20 log 10 (0.5/3) = ? 15.56 db, which is the worst case. the plot of log_error is more signifi - cant at the lower codes. 0 ?10 ?20 ?30 ?40 ?50 ?60 0 20 40 60 80 100 120 140 160 180 200 220 240 260 code, from 1 to 255 by 2 gain (db) 02618-038 log_error (code) for 8-bit figure 38 . plot of log_error conformance for odd codes only (even codes are ideal)
ad5232 data sheet rev. c | page 18 of 24 using additional int ernal , nonvolatile eemem the ad5232 contains additional internal user storage registers (eemem) for saving constants and other 8 - bit data. table 9 provides an address map of the internal nonvolat ile storage registers , which are shown in the functional block diagram as eemem1, eemem2, and bytes of user eemem. note the following about eemem function: ? rdac data stored in eemem locations are transferred to their corresponding rdac x register at power - o n or when command instruction 1 and command instruction 8 are executed. ? userx refers to internal nonvolatile eemem registers that are available to store and retrieve constants by using command instruction 3 and command instruction 9, respectively. ? the eeme m locations are one byte each (eight bits). ? execution of command instruction 1 leaves the device in the read mod e power consumption state. when the final command instruction 1 is executed, the user should perform an nop (command instruction 0) to return th e device to the low power idle state. table 9 . eemem address map eemem address (addr) eemem contents of each device eemem (addr) 0000 rdac 1 0001 rdac2 0010 user 1 0011 user 2 0100 user 3 0101 user 4 *** *** 1111 us er 14 terminal voltage ope rating range the positive v dd and negative v ss power supply of the digital potentiometer define s the boun dary conditions for proper 3 - terminal programmable resistance operations. signals present on terminal a, terminal b, and w iper terminal w that exceed v dd or v ss are clamped by a forward biased diode (see figure 39 ). the ground pin of the ad5232 device is used primarily as a digital ground referen ce that needs to be tied to the common ground of the pcb. the digital input logic signals to the ad5232 mu st be referenced to the ground (gnd) pin of the device and satisfy the minimum in put logic high level and the maximum input logic low level that are defined in the s pecifications section. an internal level shift circuit between the digital interface and the wiper switch control ensures that the common - mode v oltage range of the three terminals , terminal a, terminal b, and wiper terminal w, extends from v ss to v dd . v ss v dd a w b 02618-039 figure 39 . maximum terminal voltages set by v dd and v ss table 10. rdac and digital register addre ss map register address (addr) name of register 1 0000 rdac1 0001 rdac2 1 the rdacx registers contain data that determ in es the position of the variable resistor wiper. detailed potentiometer operat ion the actual structure of the rdac x is designed to emulate the performance of a mechanical potentiometer. the rdac x contains multiple strings of connected resistor segments, with an array of analog switches that act as the wiper connection to several points along the resisto r array. the number of points i s equal to the resolution of the device. for example, the ad5232 has 256 con - nection points, allowing it to provide better than 0.5% setability resolution. figure 40 prov ides an equivalent diagram of the con - nections between the three terminals that make up one channel of the rdac x . the sw a and sw b switches are always on, wh ereas only one of the sw(0) to sw(2 n C 1) switches is on at a time , depending on the resistance step d ecoded from the data bits. the resistance contributed by r w must be accounted for in the output resistance. b r s r s a w r s = r ab /2 n r s 02618-040 r dac wiper register and decoder notes 1. digital circuitry omitted for clarity sw a sw b sw(2 n ? 1) sw(2 n ? 2) sw(1) sw(2) figure 40 . equivalent rdac structure
data sheet ad5232 rev. c | page 19 of 24 table 11. nominal individual segment resistor values () device resolution segmented resistor size for r ab end-to-end values 10 k version 50 k version 100 k version 8-bit 78.10 390.5 781.0 programming the variable resistor rheostat operation the nominal resistances of the rdacx between terminal a and terminal b are available with values of 10 k, 50 k, and 100 k. the final digits of the part number determine the nominal resistance value; for example, 10 k = 10; 100 k = 100. the nominal resistance (r ab ) of the ad5232 vr has 256 contact points accessed by wiper terminal w, plus the terminal b contact. the 8-bit data-word in the rdacx latch is decoded to select one of the 256 possible settings. the general transfer equation, which determines the digitally programmed output resistance between wx and bx, is w ab wb rr d dr ??? 256 )( (1) where: d is the decimal equivalent of the data contained in the rdacx register. r ab is the nominal resistance between terminal a and terminal b. r w is the wiper resistance. table 12 lists the output resistance values that are set for the rdacx latch codes shown for 8-bit, 10 k potentiometers. table 12. nominal resistance value at selected codes for r ab = 10 k d (dec) r wb (d) () output state 255 10011 full scale 128 5050 midscale 1 89 1 lsb 0 50 zero scale 1 (wiper contact resistance) 1 note that in the zero-scale condition, a finite wiper resistance of 50 is present. care should be taken to limit the curre nt flow between wx and bx in this state to a maximum continuous value of 2 ma to avoid degradation or possible destruction of the internal switch metallization. intermittent current operation to 20 ma is allowed. like the mechanical potentiometer that the rdacx replaces, the ad5232 parts are totally symmetrical. the resistance between t he wip e r te r m i n a l w and te r mi n a l a a l s o pro du c e s a d i g it a l ly controlled resistance, r wa . figure 41 shows the symmetrical programmability of the various terminal connections. 100 75 50 25 0 0 64 128 192 258 code (decimal) percent of nominal end-to-end resistance (% r ab ) 02618-041 r wb r wa figure 41. symmetrical rdac operation when these terminals are used, terminal b should be tied to the wiper. setting the resistance value for r wa starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value. the general transfer equation for this operation is w ab wa rr d dr ?? ? ? 256 256 )( (2) where: d is the decimal equivalent of the data contained in the rdac register. r ab is the nominal resistance between terminal a and terminal b. r w is the wiper resistance. table 13 lists the output resistance values that are set for the rdacx latch codes shown for 8-bit, 10 k potentiometers. table 13. nominal resistance value at selected codes for r ab = 10 k d (dec) r wa (d) () output state 255 89 full scale 128 5050 midscale 1 10011 1 lsb 0 10050 zero scale the multichannel ad5232 has a 0.2% typical distribution of internal channel-to-channel r ba match. device-to-device matching is dependent on process lot and exhibits a ?40% to +20% variation. the change in r ba with temperature has a 600 ppm/c temperature coefficient.
ad5232 data sheet rev. c | page 20 of 24 programming the pote ntiometer divider voltage output operation the digital potentiometer easily generates an output voltage pro - portional to the input voltage applied to a given ter minal. for example, connectin g terminal a to 5 v and t erminal b to gnd produces an output voltage at the wiper that can be any value from 0 v to 5 v. each lsb of voltage is equal to the voltage applied across terminal a to terminal b , divided by the 2 n position resolution of the poten tiometer divider. the general equation defining the output voltage with respect to ground for any given input volt age applied to terminal a to terminal b is b ab wa a ab wb w v r d r v r d r d v + = ) ( ) ( ) ( (3 ) where r wb ( d ) can be obtained from equation 1 and r wa ( d ) can be obtained from e quation 2 . operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. here the output voltage is dependent on the ratio of the internal resistors, not the absolute value; therefore, the drift impr oves to 15 ppm/c. there is no voltag e polarity restriction between terminal a, terminal b, and wiper te rm i na l w as long as the terminal voltage (v term ) stays within v ss < v term < v dd . operation from dual supplies the ad5232 can be operated from dual supplies , enabling control of ground - referenced ac signals (s ee figure 42 for a typical circuit connection ) . ad5232 v ss gnd sdi clk ss sclk mosi gnd v dd 2v p-p 1v p-p v dd +2.5v ?2.5v cs 02618-042 microconverter figure 42 . operation from dual supplie s the internal parasitic capacitances and the external capacitive loads dominate the ac characteristics of t he rdacs . when c onfigured as a potentiometer divider, the ? 3 db band width of the ad5232bru 10 (10 k? res istor) measures 500 khz at half scale. figure 14 provides the large signal bode plot character - istics of the three resistor versions : 10 k?, 50 k?, and 100 k? (s ee figure 43 for a parasitic simulation model of the rdac circuit ) . a w 02618-043 b rdac n? c a 45pf c b 45pf c w 60pf figure 43 . rdac circuit simulation model for rdac x = 10 k? the following code provides a macro model net list for the 10 k? rdac: .param dw=255, rdac=10e3 * .subckt dpot (a,w,b) * ca a 0 {4 5e - 12} raw a w {(1 - dw/256)*rdac+50} cw w 0 60e - 12 rbw w b {dw/256*rdac+50} cb b 0 {45e - 12} * .ends dpot application programm ing examples the command sequence examples shown in table 14 to table 18 have been developed to illustrate a typical sequence of events for the various features of the ad5232 nonvolatile digital poten - tiometer. table 14 illustrates setting two dig ital potentiometers to independent data values. table 14. sdi sdo action 0x b140 0x xxxx loads 0x 40 d ata into the rdac2 register; wiper w2 moves to 1/4 full - scale p osition . 0x b080 0x b140 loads 0x 80 data into the rdac1 register; wiper w1 m oves to 1 /2 full - scale p osition . table 15 illustrates the active trimming of one potentiometer, followed by a save to nonvolatile memory (pcb calibrate). table 15. sdi sdo action 0x b040 0x xxxx loads 0x 40 data into the rdac1 register; wiper w1 moves to 1/4 full -s cale p osition . 0x e0xx 0x b040 increments the rdac1 register by 1, to 0x41; wiper w1 moves one resistor segment a way from terminal b . 0x e0xx 0x e0xx increments the rdac1 register by 1 , to 0x 42 ; wiper w1 moves one more resistor segment a way from terminal b. continue until desired the wiper position is reached. 0x 20xx 0x e0xx saves the rdac1 register data into the corresponding nonvolatile eemem1 m emory : addr = 0x 0 .
data sheet ad5232 rev. c | page 21 of 24 table 16 illustrates using the left shift-by-one to change circuit gain in 6 db steps. table 16. sdi sdo action 0xc1xx 0xxxxx moves wiper w2 to double the present data value contained in the rdac2 register in the direction of terminal a. 0xc1xx 0xxxxx moves wiper w2 to double the present data value contained in the rdac2 register in the direction of terminal a. table 17 illustrates storing additional data in nonvolatile memory. table 17. sdi sdo action 0x3280 0xxxxx stores 0x80 data in spare eemem location, user1. 0x3340 0xxxxx stores 0x40 data in spare eemem location, user2. table 18 illustrates reading back data from various memory locations. table 18. sdi sdo action 0x94xx 0xxxxx prepares data read from user3 location. (user3 is already loaded with 0x80.) 0x00xx 0xxx80 instruction 0 (nop) sends 16-bit word out of sdo where the last eight bits contain the contents of user3 location. the nop command ensures that the device returns to the idle power dissipation state. equipment customer start-up sequence for a pcb calibrated unit with protected settings 1. for the pcb setting, tie wp to gnd to prevent changes in the pcb wiper set position. 2. set power v dd and v ss with respect to gnd. 3. as an optional step, strobe the pr pin to ensure full power- on preset of the wiper register with eemem contents in unpredictable supply sequencing environments. flash/eemem reliability the flash/ee memory array on the ad5232 is fully qualified for two key flash/ee memory characteristics: namely, flash/ee memory cycling endurance and flash/ee memory data retention. endurance quantifies the ability of the flash/ee memory to be cycled through many program, read, and erase cycles. in real terms, a single endurance cycle is composed of four independent, sequential events. these events are defined as follows: 1. initial page erase sequence 2. read/verify sequence 3. byte program sequence 4. second read/verify sequence during reliability qualification, flash/ee memory is cycled from 0x00 to 0xff until a first fail is recorded, signifying the endurance limit of the on-chip flash/ee memory. as indicated in the specifications section, the ad5232 flash/ee memory endurance qualification has been carried out in accor- dance with jedec std. 22, method a117 over the industrial temperature range of ?40c to +85c. the results allow the specification of a minimum endurance figure over supply and temperature of 100,000 cycles, with an endurance figure of 700,000 cycles being typical of operation at 25c. retention quantifies the ability of the flash/ee memory to retain its programmed data over time. again, the ad5232 has been qualified in accordance with the formal jedec retention lifetime specification (a117) at a specific junction temperature of t j = 55c. as part of this qualification procedure, the flash/ee memory is cycled to its specified endurance limit, as described previously, before data retention is characterized. this means that the flash/ee memory is guaranteed to retain its data for its full specified retention lifetime every time the flash/ee memory is repro-grammed. it should also be noted that retention lifetime, based on an activation energy of 0.6 ev, derates with t j , as shown in figure 44. 300 250 200 150 100 50 0 40 50 60 70 80 90 100 110 t j junction temperature (c) retention (years) 02618-044 adi typical performance at t j = 55c figure 44. flash/ee memory data retention evaluation board analog devices, inc., offers a user-friendly EVAL-AD5232-SDZ evaluation kit that can be controlled by a personal computer through a printer port. the driving program is self-contained; no programming languages or skills are needed.
ad5232 data sheet rev. c | page 22 of 24 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 45. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters ordering guide model 1 number of channels end-to-end r ab (k) temperature range package description package option ordering quantity branding 2 ad5232bru10 2 10 ?40c to +85c 16-lead tssop ru-16 96 5232b10 ad5232bru10-reel7 2 10 ?40c to +85c 16-lead tssop ru-16 1,000 5232b10 ad5232bruz10 2 10 ?40c to +85c 16-lead tssop ru-16 96 5232b10 ad5232bruz10-reel7 2 10 ?40c to +85c 16-lead tssop ru-16 1,000 5232b10 ad5232bru50 2 50 ?40c to +85c 16-lead tssop ru-16 96 5232b50 ad5232bruz50 2 50 ?40c to +85c 16-lead tssop ru-16 96 5232b50 ad5232bruz50-reel7 2 50 ?40c to +85c 16-lead tssop ru-16 1,000 5232b50 ad5232bru100-reel7 2 100 ?40c to +85c 16-lead tssop ru-16 1,000 5232bc ad5232bruz100 2 100 ?40c to +85c 16-lead tssop ru-16 96 5232bc ad5232bruz100-rl7 2 100 ?40c to +85c 16-lead tssop ru-16 1,000 5232bc EVAL-AD5232-SDZ 10 evaluation board 1 1 z = rohs compliant part. 2 line 1 contains the analog devices logo, followed by the date code: yyww. line 2 contains the model number, followed by the en d-to-end resistance value. (note that c = 100 k). or line 1 contains the model number. line 2 contains the analog devices logo, followed by the end-to-end resistance value. line 3 contains the date code: yyww.
data sheet ad5232 rev. c | page 23 of 24 notes
ad5232 d ata sheet rev. c | page 24 of 24 notes ? 2001 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d02618 - 0 - 11/13(c)

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